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| general description the MAX7359 i 2 c interfaced peripheral provides micro- processors with management of up to 64 key switches.key codes are generated for each press and release of a key for easier implementation of multiple key entries. key inputs are monitored statically, not dynamically, to ensure low-emi operation. the switches can be metallic or resistive (carbon) with up to 5k ? of resistance. the MAX7359 features autosleep and autowake to fur-ther minimize the power consumption of the device. the autosleep feature puts the device in a low-power state (1? typ) after a sleep timeout period. the autowake feature configures the MAX7359 to return to normal operating mode from sleep upon a key press. the key controller debounces and maintains a fifo of key-press and release events (including autorepeat, if enabled). an interrupt ( int ) output can be configured to alert key presses either as they occur, or at maximum rate.any of the column drivers (col2/port2?ol7/port7) or the int , if not used, can function as a general-pur- pose output (gpo).the MAX7359 is offered in small, 24-pin tqfn (3.5mm x 3.5mm) and 25-bump wlp (2.31mm x 2.31mm) pack- ages for cell phones, pocket pcs, and other portable consumer electronic applications. the MAX7359 oper- ates over the -40? to +85? temperature range. applications cell phonespdas handheld games portable consumer electronics features ? optional key release detection on all keys ? monitor up to 64 keys ? +1.62v to +3.6v operation ? autosleep and autowake to minimize currentconsumption ? under 1 a sleep current ? fifo queues up to 16 debounced key events ? key debounce time user configurable from 9msto 40ms ? low-emi design uses static matrix monitoring ? hardware interrupt at the fifo level or at the endof definable time period ? up to seven open-drain logic outputs availablecapable of driving leds ? 400kbps, 5.5v-tolerant, 2-wire serial interface ? selectable 2-wire, serial-bus timeout ? four i 2 c address choices ? small, 24-pin tqfn package (3.5mm x 3.5mm) , or 25-pin wlp package (2.31mm x 2.31mm) MAX7359 2-wire interfaced low-emi key switch controller/gpo ________________________________________________________________ maxim integrated products 1 ordering information 19-0850; rev 4; 6/10 evaluation kit available part temp range pin-package MAX7359etg+ -40? to +85? 24 tqfn-ep* MAX7359ewa+ -40? to +85? 25 wlp + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. MAX7359 v cc col_ gnd 8 sclsda ad0 row_ 8 switch array, up to 64 switches input +1.62v to +3.6v int typical application circuits typical application circuits continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations MAX7359 1920 21 22 12 3456 18 17 16 15 14 13 2324 1211 10 98 7 int n.c. v cc col7/port7 row1 row2row3 col3/port3col4/port4 row4row5 sclsda gnd i.c.col0 row0 col1col5/port5 col2/port2col6/port6 row6 row7 ad0 top view tqfn (3.5mm x 3.5mm) + ep* *ep = exposed pad. pin configurations continued at end of data sheet. downloaded from: http:///
MAX7359 2-wire interfaced low-emi key switch controller/gpo 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.)v cc ..........................................................................-0.3v to +4v col2/port2?ol7/port7 ....................................-0.3v to +4v sda, scl, ad0, int .................................................-0.3v to +6v all other pins ..............................................-0.3v to (v cc + 0.3v) dc current on col2/port2?ol7/port7 ......................25ma gnd current .......................................................................80ma continuous power dissipation (t a = +70?) 24-pin tqfn (derate 15.4mw/? above +70?) ........1229mw 25-bump wlp (derate 19.2mw/? above +70?)......1194mw junction-to-case thermal resistance ( j c ) (note 1) 24-pin tqfn.................................................................5.4?/w 25-bump wlp ...............................................................17?/w junction-to-ambient thermal resistance ( j a ) (note 1) 24-pin tqfn...............................................................65.1?/w 25-bump wlp ...............................................................53?/w operating temperature range (t min to t max ) .....-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (tqfn only, soldering, 10s) ..............+300? soldering temperature (reflow) .......................................+260? electrical characteristics(v cc = +1.62v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +2.5v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units operating supply voltage v cc 1.62 3.60 v all key switches open, oscillator running,col2?ol7 configured as key switches 25 60 operating supply current i cc n keys pressed (25 + 20 x n) ? sleep-mode supply current i sl 0.6 5 ? por 1.0 1.6 v por hysteresis porhyst v cc rising 42 mv key-switch source current i key 20 35 ? key-switch source voltage v key operating mode 0.42 0.55 v key-switch resistance r key (note 4) 5 k startup time from shutdown t start 2 2.4 ms output low voltagecol2/port2 to col7/port7 v olport i sink = 10ma 0.2 v int output v olint i sink = 10ma 0.5 v oscillator frequency f osc 64 khz serial-interface specifications serial bus timeout t out with bus timeout enabled 10 40 ms input high voltagesda, scl, ad0 v ih 0.7 x v cc v input low voltagesda, scl, ad0 v il 0.3 x v cc v output low voltage sda v olport i sink = 10ma 0.4 v input leakage current v cc = 0v to +6v -1 +1 ? note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo _______________________________________________________________________________________ 3 i 2 c timing characteristics (v cc = +1.62v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +2.5v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units input capacitance(scl, sda, ad0) c in (notes 4, 5) 10 pf scl serial-clock frequency f scl bus timeout disabled 0 400 khz bus free time between a stopand a start condition t buf 1.3 ? hold time (repeated) startcondition t hd , sta 0.6 ? repeated start conditionsetup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 6) 0.9 ? data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of both sda and sclsignals, receiving t r (notes 4, 5) 20 + 0.1c b 300 ns fall time of both sda and sclsignals, receiving t f (notes 4, 5) 20 + 0.1c b 300 ns fall time of sda transmitting t f, tx (notes 4, 7) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (notes 4, 8) 50 ns c ap aci ti ve load for e ach bus li ne c b (note 4) 400 pf note 2: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design. note 3: all digital inputs at v cc or gnd. note 4: guaranteed by design. note 5: c b = total capacitance of one bus line in pf. t r and t f measured between +0.3v cc and +0.7v cc . note 6: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 7: i sink 6ma. note 8: input filters on the sda, scl, and ad0 inputs suppress noise spikes less than 50ns. downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 4 _______________________________________________________________________________________ 0 100 50 200150 250 300 01 0 1 5 52 0 2 5 3 0 gpo port output low voltage vs. sink current MAX7359 toc01 i sink (ma) v ol (mv) v cc = +2.4v t a = +85 c t a = +25 c t a = -40 c 0 50 100 200150 250 300 01 0 51 5 2 0 2 5 3 0 gpo port output low voltage vs. sink current MAX7359 toc02 i sink (ma) v ol (mv) t a = +85 c t a = -40 c v cc = +3.0v t a = +25 c 0 50 200150 100 250 300 01 0 51 5 2 0 2 5 3 0 gpo port output low voltage vs. sink current MAX7359 toc03 i sink (ma) v ol (mv) v cc = +3.6v t a = +85 c t a = -40 c t a = +25 c 15 20 3025 35 40 1.6 2.4 2.0 2.8 3.2 3.6 supply current vs. supply voltage MAX7359 toc04 supply voltage (v) supply current ( a) autosleep = off t a = +85 c t a = -40 c t a = +25 c key-switch source current vs. supply voltage MAX7359 toc05 supply voltage (v) key-switch source current ( a) 3.2 2.8 2.4 2.0 20.5 21.0 21.5 22.020.0 1.6 3.6 col0 = gnd t a = +85 c t a = -40 c t a = +25 c 2.01.5 1.0 0.5 0 1.6 2.6 2.1 3.1 3.6 sleep mode supply current vs. supply voltage MAX7359 toc06 supply voltage (v) shutdown supply current ( a) typical operating characteristics (v cc = +2.5v, t a = +25?, unless otherwise noted.) downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo _______________________________________________________________________________________ 5 64khz oscillator por bus timeout i 2 c interface control registers fifo key scan current source column drives open- drain row drives column enable gpo enable row enable current detect col0 col1 col2* col3* col4* col5* col6* col7* row0 row1 row2 row3 row4 row5 row6 row7 intsda scl *gpo MAX7359 functional block diagram downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 6 _______________________________________________________________________________________ detailed description the MAX7359 is a microprocessor peripheral low-noisekey-switch controller that monitors up to 64 key switches with optional autorepeat, and key events are presented in a 16-byte fifo. key-switch functionality can be traded to provide up to six open-drain logic outputs. the MAX7359 features an automatic sleep mode and automatic wakeup that further reduce supply current con- sumption. the MAX7359 can be configured to enter sleep mode after a programmable time following a key event. the fifo content is maintained during sleep mode and can be read in sleep mode. the MAX7359 does not enter autosleep when a key is held down. the autowake feature takes the MAX7359 out of sleep mode following a key- press event. autosleep and autowake can be disabled. interrupt requests can be configured to be issued on aprogrammable number of fifo entries, or can be set to a period of time to prevent overloading the micro- processor with too many interrupts. the key-switch sta- tus can be checked at any time by reading the key-switch fifo. a 1-byte read access returns both the next key-event in the fifo (if there is one) and the fifo status, so it is easy to operate the MAX7359 by polling. if the int pin is not required, it can be config- ured as an open-drain general-purpose output (gpo)capable of driving an led. if the application requires fewer keys to be scanned, up to six of the key-switch outputs can be configured as open-drain gpos capable of driving leds. for each key-switch output used as a gpo, the number of key switches that can be scanned is reduced by eight. pin description pin tqfn wlp name function 1a 1 row2 row input from key matrix. leave row2 unconnected or connect to gnd if unused. 2a 2 row3 row input from key matrix. leave row3 unconnected or connect to gnd if unused. 3a 3 col3/port3 column output to key matrix or gpo. leave col3/port3 unconnected if unused. 4b 3 col4/port4 column output to key matrix or gpo. leave col4/port4 unconnected if unused. 5a 4 row4 row input from key matrix. leave row4 unconnected or connect to gnd if unused. 6a 5 row5 row input from key matrix. leave row5 unconnected or connect to gnd if unused. 7b 5 row6 row input from key matrix. leave row6 unconnected or connect to gnd if unused. 8b 4 row7 row input from key matrix. leave row7 unconnected or connect to gnd if unused. 9c 5 col6/port6 column output to key matrix or gpo. leave col6/port6 unconnected if unused. 10 c4 col5/port5 column output to key matrix or gpo. leave col5/port5 unconnected if unused. 11 d5 col2/port2 column output to key matrix or gpo. leave col2/port2 unconnected if unused. 12 e5 col1 column output to key matrix. leave col1 unconnected if unused. 13 e4 col0 column output to key matrix. leave col0 unconnected if unused. 14 d4 i.c. internally connected. connect to gnd for normal operation. 15 d3 gnd ground 16 e3 ad0 adddress input. ado selects up to four device slave addresses (table 10). 17 e2 sda i 2 c-compatible, serial-data i/o 18 d2 scl i 2 c-compatible, serial-clock input 19 e1 int active-low interrupt output. int is open drain. 20 d1 v cc positive supply voltage. bypass v cc to gnd with a 0.047? or higher ceramic capacitor. 21 c2, c3 n.c. no connection. not internally connected. 22 c1 col7/port7 column output to key matrix or gpo. leave col7/port7 unconnected is unused. 23 b2 row0 row input from key matrix. leave row0 unconnected or connect to gnd if unused. 24 b1 row1 row input from key matrix. leave row1 unconnected or connect to gnd if unused. ep exposed pad (tqfn only). ep internally is connected to gnd. connect ep to a ground planeto increase thermal performance. downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo _______________________________________________________________________________________ 7 pin col0 col1 col2/port2 col3/port3 col4/port4 col5/port5 col6/port6 col7/port7 row0 key 0 key 8 key 16 key 24 key 32 key 40 key 48 key 56 row1 key 1 key 9 key 17 key 25 key 33 key 41 key 49 key 57 row2 key 2 key 10 key 18 key 26 key 34 key 42 key 50 key 58 row3 key 3 key 11 key 19 key 27 key 35 key 43 key 51 key 59 row4 key 4 key 12 key 20 key 28 key 36 key 44 key 52 key 60 row5 key 5 key 13 key 21 key 29 key 37 key 45 key 53 key 61 row6 key 6 key 14 key 22 key 30 key 38 key 46 key 54 key 62 row7 key 7 key 15 key 23 key 31 key 39 key 47 key 55 key 63 table 1. key-switch mapping address code (hex) read/write power-up value (hex) register function description 0x00 read only 0x3f keys fifo read fifo key scan data out 0x01 r/ w 0x0a configuration power down, key release enable, autowakeup, andi 2 c timeout enable 0x02 r/ w 0xff debounce key debounce time setting and gpo enable 0x03 r/ w 0x00 interrupt int frequency setting 0x04 r/ w 0xfe ports ports 2? and int gpo control 0x05 r/ w 0x00 key repeat delay and frequency for key repeat 0x06 r/ w 0x07 sleep idle time to autosleep table 2. register address map and power-up condition key-scan controller key inputs are scanned statically, not dynamically, toensure low-emi operation. as inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes. the key controller debounces and maintains a fifo of key-press and release events (including autorepeated key presses, if autorepeat is enabled). table 1 shows keys order. _____________________initial power-up on power-up, all control registers are set to power-upvalues and the MAX7359 is in sleep mode (table 2). registers description keys fifo register (0x00) the keys fifo register contains the information pertain-ing to the status of the keys fifo, as well as the key events that have been debounced (table 3). bits d0 to d5 denote which of the 64 keys have been debouncedand the keys are numbered as in table 1. d7 indicates if there is more data in the fifo except when d5:d0 indicate key 63 or key 62. when d5:d0 indicate key 63 or key 62, the host should read one more time to determine whether there is more data in fifo. it is better to use key 62 and key 63 for rarely used keys. d6 indicates if it is a key-press or release event except when d5:d0 indicate key 63 or key 62. reading the key-scan fifo clears the interrupt int depending on the setting of bit d5 in the configurationregister (0x01). configuration register (0x01) the configuration register controls the i 2 c bus timeout feature, enables key release detection, enables autowake,and determines how int should be deasserted. by writing to bit d7, you can put the MAX7359 into sleep mode oroperating mode, however, autosleep and autowake, when enabled, also change the status of this bit (table 4). downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 8 _______________________________________________________________________________________ keys fifo register data special function d7 d6 d5 d4 d3 d2 d1 d0 the key number indicated by d5:d0 is a key event. d7is always for a key press of key 62 and key 63. when d7 is 0, the key read is the last data in the fifo. when d7 is 1, there is more data in the fifo. when d6 is 1, key data read from fifo is a key release. when d6 is 0, key data read from fifo is a key press. fifo empty flag key release flag xxxxxx fifo is empty. 0 0 111111 fifo is overflow. continue to read data in fifo. 0 1 111111 key 63 is pressed. read one more time to determinewhether there is more data in fifo. 10111111 key 63 is released. read one more time to determinewhether there is more data in fifo. 11111111 key repeat. indicates the last data in fifo. 0 0 111110 key repeat. indicates more data in fifo. 0 1 111110 key 62 is pressed. read one more time to determinewhether there is more data in fifo. 10111110 key 62 is released. read one more time to determinewhether there is more data in fifo. 11111110 table 3. keys fifo register format (0x00) downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo _______________________________________________________________________________________ 9 register bit description value function default value 0 sleep mode d7 sleep 1 operating mode i 2 c write, autosleep and autowakeup all can change this bit. this bit can be read back by i 2 c any time for current status. 0 d6 reserved 0 this bit must always be 0. improper operationmay result by writing a 1 to this location. 0 0 int cleared when fifo empty d5 interrupt 1 int cleared after host read. in this mode, i 2 c should read fifo until interrupt condition removed, or further intmay be lost. 0 d4 reserved 0 this bit must always be 0. improper operationmay result by writing a 1 to this location. 0 0 disable d3 key release enable 1 enable 1 d2 reserved 0 this bit must always be 0. improper operationresults by writing a 1 to this location. 0 0 disable d1 wakeup 1 key press wakeup enable 1 0i 2 c timeout enabled d0 timeout enable 1i 2 c timeout disabled 0 table 4. configuration register format (0x01) downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 10 ______________________________________________________________________________________ debounce register (0x02) the debounce register sets the time for each debouncecycle, as well as setting whether the gpo ports are enabled or disabled. bits d0 through d4 set the debounce time in increments of 1ms starting at 9ms and ending at 40ms (table 5). bits d5 through d7 setwhich of the gpo ports is enabled. note the gpo ports can be enabled only in the combinations shown in table 5, from all disabled to all enabled. register data d7 d6 d5 d4 d3 d2 d1 d0 register description ports enable debounce time debounce time is 9ms x x x 0 0 0 0 0 debounce time is 10ms x x x 0 0 0 0 1 debounce time is 11ms x x x 0 0 0 1 0 debounce time is 12ms x x x 0 0 0 1 1 .. . debounce time is 37ms x x x 1 1 1 0 0 debounce time is 38ms x x x 1 1 1 0 1 debounce time is 39ms x x x 1 1 1 1 0 debounce time is 40ms x x x 1 1 1 1 1 gpo ports disabled (full key-scan functionality) 0 0 0 x x x x x gpo port 7 enabled 0 0 1 x x x x x gpo ports 7 and 6 enabled 0 1 0 x x x x x gpo ports 7, 6, and 5 enabled 0 1 1 x x x x x gpo ports 7, 6, 5, and 4 enabled 1 0 0 x x x x x gpo ports 7, 6, 5, 4, and 3 enabled 1 0 1 x x x x x gpo ports 7, 6, 5, 4, 3, and 2 enabled 1 1 xxxxxx power-up default setting 1 1 111111 table 5. debounce register format (0x02) downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo ______________________________________________________________________________________ 11 interrupt register (0x03) the interrupt register contains information related to thesettings of the interrupt request function, as well as the status of the int output, which can also be configured as a gpo. if bits d0 through d7 are set to 0x00, the int out- put is configured as a gpo that is controlled by bit d1 inthe port register. there are two types of interrupts, the fifo based-interrupt and time-based interrupt. the time- based interrupt can be configured to assert int after a number of debounce cycles. by setting bits d0 through d4 to an appropriate value, the interrupt can be assertedat the end of the selected number of debounce cycles following a key event (table 6). this number ranges from 1 to 31 debounce cycles. the fifo based interrupt can be configured to assert int when there are between 4 through 16 key events stored in the fifo. bits d7 throughd5 set the fifo based interrupt. both interrupts can be configured simultaneously and int asserts depending on which condition is met first. int deasserts depending on the status of bit d5 in the configuration register. register data d7 d6 d5 d4 d3 d2 d1 d0 register description fifo-based int time-based int int used as gpo 00000000 fifo based int disabled 0 0 0 not all zero int asserts every debounce cycles 00000001 int asserts every 2 debounce cycles 00000010 .. . int asserts every 29 debounce 00011101 int asserts every 30 debounce 00011110 int asserts every 31 debounce 00011111 time based int disabled not all zero 0 0 0 0 0 int asserts when fifo has 2 key events 0 0 1 0 0 0 0 0 int asserts when fifo has 4 key events 0 1 0 0 0 0 0 0 int asserts when fifo has 6 key events 0 1 1 0 0 0 0 0 .. . int asserts when fifo has 16 key events 1 1 1 0 0 0 0 0 both time base and fifo based interrupts active not all zero not all zero power-up default setting 0 0 000000 table 6. interrupt register format (0x03) ports register (0x04) the ports register sets the values of ports 2 through 7 andthe int port when configured as open-drain gpos. the settings in this register are ignored for ports not config-ured as gpos, and a read from this register returns the values stored in the register (table 7). autorepeat register (0x05) the MAX7359 autorepeat feature notifies the host that atleast one key has been pressed for a continuous period of time. the autorepeat register enables or disables this feature, sets the time delay after the last key event before the key repeat code (0x7e) is entered into the fifo, and sets the frequency at which the key repeat code isentered into the fifo thereafter. bit d7 specifies whether the autorepeat function is enabled with 0 denoting autorepeat disabled and 1 denoting autorepeat enabled. bits d0 through d3 specify the autorepeat delay in terms of debounce cycles ranging from eight debounce cycles to 128 debounce cycles (table 8). bits d4 through d6 specify the autorepeat rate or frequency ranging from 4 to 32 debounce cycles. when autorepeat is enabled, holding the key pressed results in a key repeat event that is denoted by 0x7e. the key being pressed does not show up again in the fifo. downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 12 ______________________________________________________________________________________ register bit description value function default value 0 clear port 7 low d7 port 7 control 1 set port 7 high (high impedance) 1 0 clear port 6 low d6 port 6 control 1 set port 6 high (high impedance) 1 0 clear port 5 low d5 port 5 control 1 set port 5 high (high impedance) 1 0 clear port 4 low d4 port 4 control 1 set port 4 high (high impedance) 1 0 clear port 3 low d3 port 3 control 1 set port 3 high (high impedance) 1 0 clear port 2 low d2 port 2 control 1 set port 2 high (high impedance) 1 0 clear port int low d1 int port control 1 set port int high (high impedance) 1 d0 reserved 0 0 table 7. ports register format (0x04) register data d7 d6 d5 d4 d3 d2 d1 d0 register description enable autorepeat rate autorepeat delay autorepeat is disabled 0 x x x x x x x autorepeat is enabled 1 autorepeat rate autorepeat delay key-switch autorepeat delay is 8 debounce cycles 1 x x x 0 0 0 0 key-switch autorepeat delay is 16 debounce cycles 1 x x x 0 0 0 1 key-switch autorepeat delay is 24 debounce cycles 1 x x x 0 0 1 0 .. . key-switch autorepeat delay is 112 debounce cycles 1 x x x 1 1 0 1 key-switch autorepeat delay is 120 debounce cycles 1 x x x 1 1 1 0 key-switch autorepeat delay is 128 debounce cycles 1 x x x 1 1 1 1 key-switch autorepeat frequency is 4 debounce cycles 1 0 0 0 x x x x key-switch autorepeat frequency is 8 debounce cycles 1 0 0 1 x x x x key-switch autorepeat frequency is 12 debounce cycles 1 0 1 0 x x x x .. . key switch autorepeat frequency is 32 debounce cycles 1 1 1 1 x x x x power-up default setting 0 0 0 0 0 0 0 0 table 8. autorepeat register format (0x05) downloaded from: http:/// only one autorepeat code is entered into the fifo, regard-less of the number of keys pressed. the autorepeat code continues to be entered in the fifo at the frequency set by the bits d4?1 until another key event is recorded. following the key-release event, if any keys are still pressed, the MAX7359 restarts the autorepeat sequence. autosleep register (0x06) autosleep puts the MAX7359 in sleep mode to draw minimalcurrent. when enabled, the MAX7359 enters sleep mode if no keys are pressed for the autosleep time (table 9). sleep mode in sleep mode, the MAX7359 draws minimal current.switch matrix current sources are turned off and pulled up to v cc . writing a 0 to d7 in the configuration register (0x01) puts the device in sleep mode. writing a 1 to d7or a key press, when the part is programmed to autowake, can take the MAX7359 out of sleep mode. bit d7 in the configuration register gives the sleep mode status and can be read anytime. the fifo data is maintained while in sleep mode. autowake key presses initiate autowake and the MAX7359 goesinto operating mode. key presses that autowake the MAX7359 are not lost. when a key is pressed while the MAX7359 is in sleep mode, all analog circuitry, includ- ing switch matrix current sources, turn on in 2ms. the initial key needs to be pressed for 2ms plus the debounce time to be stored in the fifo. autowakeup can be disabled by writing a 0 to d1 in the configura- tion register (0x01). serial interface figure 1 shows the 2-wire serial interface timing details. serial addressing the MAX7359 operates as a slave that sends andreceives data through an i 2 c-compatible 2-wire inter- face. the interface uses a serial-data line (sda) and aserial-clock line (scl) to achieve bidirectional commu- nication between master(s) and slave(s). a master (typ- ically a microcontroller) initiates all data transfers to and from the MAX7359 and generates the scl clock that synchronizes the data transfer. the MAX7359? sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on sda. the MAX7359? scl line operatesonly as an input. a pullup resistor is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start (s) condition (figure 2) sent by a master, followed by the MAX7359 7- bit slave address plus r/ w bit, a register address byte, 1 or more data bytes, and finally a stop (p) condition. start and stop conditions both scl and sda remain high when the interface is notbusy. a master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse(figure 3). the data on sda must remain stable while scl is high. MAX7359 2-wire interfaced low-emi key switch controller/gpo ______________________________________________________________________________________ 13 register register data reserved autoshutdown time autosleep register d7 d6 d5 d4 d3 d2 d1 d0 no autosleep 0 0 0 0 0 0 0 0 autosleep for (ms) 8192 0 0 0 0 0 0 0 1 4096 0 0 0 0 0 0 1 0 2048 0 0 0 0 0 0 1 1 1024 0 0 0 0 0 1 0 0 5 1 2 00000 1 0 1 2 5 6 00000 1 1 0 2 5 6 00000 1 1 1 power-up default settings 0 0 0 0 0 1 1 1 table 9. autosleep register format (0x06) downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 14 ______________________________________________________________________________________ sda scl t hd, sta t low t high t r t f t su, dat t su, sta t su, sto t buf t hd, sta t hd, dat start condition stop condition start condition repeated start condition t f t f, tx t r figure 1. 2-wire serial interface timing details sda scl start condition stop condition s p figure 2. start and stop conditions sda scl data line stable; data valid change of data allowed figure 3. bit transfer downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo ______________________________________________________________________________________ 15 MAX7359 acknowledge the acknowledge bit is a clocked 9th bit (figure 4),which the recipient uses to handshake receipt of each byte of data. thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, so the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the MAX7359, the MAX7359 generates the acknowledge bit because the MAX7359 is the recipient. when the MAX7359 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. slave addresses the MAX7359 has a 7-bit long slave address (figure 5).the bit following a 7-bit slave address is the r/ w bit, which is low for a write command and high for a readcommand. the first 4 bits (msbs) of the MAX7359 slave address are always 0111. slave address bits a3, a2, and a1 correspond, by the matrix in table 10, to the states of the device address input ad0, and a0 corresponds to the r/ w bit. the ad0 input can be connected to any of four signals: gnd, v cc , sda, or scl, giving four possi- ble slave address pairs, allowing up to four MAX7359devices to share the bus. because sda and scl are dynamic signals, care must be taken to ensure that ad0 transitions no sooner than the signals on the sda and scl pins. the MAX7359 monitors the bus continuously, waiting fora start condition followed by its slave address. when the MAX7359 recognizes its slave address, it acknowl- edges and is then ready for continued communication. bus timeout the MAX7359 features a 20ms minimum bus timeout onthe 2-wire serial interface, largely to prevent the MAX7359 from holding the sda i/o low during a read transaction if the scl hangs for any reason before a seri- al transaction has been completed. bus timeout operates by causing the MAX7359 to internally terminate a serial transaction, either read or write, if scl low exceeds 20ms. after a bus timeout, the MAX7359 waits for a valid start condition before responding to a consecutive transmission. this feature can be enabled or disabled under user control by writing to the configuration register (table 4). device address pin ad0 a7 a6 a5 a4 a3 a2 a1 a0 g n d 0111000r / w v cc 0111010r / w s d a 0111100r / w s c l 0111110r / w table 10. 2-wire interface address map sda scl 01 1a 3a 2a 1 1 msb lsb ack r/w figure 5. slave address scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s figure 4. acknowledge downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo 16 ______________________________________________________________________________________ saa p 0 slave address command byte d7 d6 d5 d4 d3 d2 d1 d0 command byte is stored on receipt of acknowledge condition acknowledge from MAX7359 acknowledge from MAX7359 r/w figure 6. command byte received saaa p 0 slave address command byte data byte 1 byte autoincrement command byte address d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from MAX7359 acknowledge from MAX7359 acknowledge from MAX7359 r/w figure 7. command and single data byte received MAX7359 message format for writing the key-scan controller a write to the MAX7359 comprises the transmission of theslave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information isthe command byte. the command byte determines which register of the MAX7359 is to be written by the next byte, if received. if a stop condition is detected after the com- mand byte is received, the MAX7359 takes no further action (figure 6) beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the MAX7359 selected by the command byte (figure 7). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent MAX7359 internal registers (table 7) because the command byte address generally autoin- crements (table 11). message format for reading the key-scan controller the MAX7359 is read using the MAX7359? internallystored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. the pointer generally autoincrements after each data byte is read using the same rules as for a write (table 11). thus, a read is initiated by first con- figuring the MAX7359? command byte by performing a write (figure 6). the master can now read n consecu-tive bytes from the MAX7359, with the first data byte being read from the register addressed by the initial- ized command byte. when performing read-after-write verification, remember to reset the command byte? address because the stored command byte address is generally autoincremented after the write (figure 8, table 11). operation with multiple masters if the MAX7359 is operated on a 2-wire interface with mul-tiple masters, a master reading the MAX7359 should use a repeated start between the write that sets the MAX7359? address pointer, and the read(s) that takes the data from the location(s). this is because it is possible for master 2 to take over the bus after master 1 has set up the MAX7359? address pointer but before master 1 has read the data. if master 2 subsequently resets the MAX7359? address pointer, master 1? read may be from an unexpected location. register function address code (hex) autoincrement address (hex) keys fifo 0x00 0x00 autoshutdown 0x06 0x00 all other 0x01 thru 0x05 addr + 0x01 table 11. autoincrement rules downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo ______________________________________________________________________________________ 17 MAX7359 command address autoincrementing address autoincrementing allows the MAX7359 to beconfigured with fewer transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the MAX7359 generally increments after each data byte is written or read (table 11). autoincrement only works when doing a multiburst read or write. applications information ghost-key elimination ghost keys are a phenomenon inherent with key-switchmatrices. when three switches located at the corners of a matrix rectangle are pressed simultaneously, the switch that is located at the last corner of the rectangle (the ghost key) also appears to be pressed. this occurs because the potentials at the two sides of the ghost-key switch are identical due to the other three connections the switch is electrically shorted by the combination of the other three switches (figure 9). because the key appears to be pressed electrically, it is impossible to detect which of the four keys is the ghost key. the MAX7359 employs a proprietary scheme that detects any three-key combination that generates a fourth ghost key, and does not report the third key that causes a ghost key event. this means that although ghost keys are never reported, many combinations of three keys are effectively ignored when pressed at the same time. applications requiring three-key combina- tions (such as MAX7359 2-wire interfaced low-emi key switch controller/gpo 18 ______________________________________________________________________________________ regular key-press event ghost-key event key-switch matrix figure 9. ghost-key phenomenon key-switch matrix key-switch matrix examples of valid three-key combinations figure 10. valid three-key combinations MAX7359 MAX7359 row0row1 row2 row3 row4 row5 row6 row7 col0 col1 col2/port2 col3/port3 col4/port4 col5/port5 gnd v cc col6/port6 col7/port7 ad0 scl sda int scl sda int +1.8v gnd c v cc +3.3v +3.3v +5v key 0 key 1 key 2key 3 key 4 key 5 key 6 key 7 key 8key 9 key 10 key 11 key 12 key 13 key 14 key 15 key 16key 17 key 18 key 19 key 20 key 21 key 22 key 23 key 24key 25 key 26 key 27 key 28 key 29 key 30 key 31 key 32key 33 key 34 key 35 key 36 key 37 key 38 key 39 key 40key 41 key 42 key 43 key 44 key 45 key 46 key 47 typical application circuits (continued) downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo ______________________________________________________________________________________ 19 MAX7359 chip information process: bicmos package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 24 tqfn-ep t243a3+1 21-0188 25 wlp w252f2+1 21-0453 pin configurations (continued) MAX7359 top view (bumps on bottom) ab cd wlp (2.31mm 2.31mm) e row3 2 row0 n.c. scl sda row4 4 row7 col5/ port5 i.c. col0 row2 1 row1 col7/ port7 v cc int row5 row6 col6/ port6 col2/ port2 5 col1 col3/ port3 3 col4/ port4 n.c. gnd ad0 + downloaded from: http:/// MAX7359 2-wire interfaced low-emi key switch controller/gpo maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/07 initial release 1 4/08 changed scl device address for a1 in table 10 15 2 2/09 added port capacitance and software reset sections to applications information section 17 3 8/09 added wlp package information 1, 2, 3, 19 4 6/10 updated absolute maximum ratings and notes 6 and 8 (now notes 5 and 7) in electrical characteristics 2, 3 downloaded from: http:/// |
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